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Exploring Energy Efficient DSP Design for an Audio ASIC

Raben, K.T. (2022) Exploring Energy Efficient DSP Design for an Audio ASIC.

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Full Text Status:Access to this publication is restricted
Embargo date:1 May 2024
Abstract:With more and more consumer audio products becoming portable, maximizing battery lifetime has become extremely important. This drives the need for more energy-efficient Application Specific Integrated Circuits (ASIC) with a focus on audio. Often these chips have a Digital Signal Processor (DSP) section in their design to manipulate the audio signal before being amplified. Such a DSP typically implements various signal processing algorithms. This thesis explores how certain architectural choices influence the energy efficiency of such a DSP. A focus is laid on how the time-area trade off affects the energy consumption of a Finite Impulse Response (FIR) filter implementation. Through the use of Clash[1], a hardware description language with strong abstraction mechanisms, a method is presented where the amount of parallelism in a processor-like architecture can be controlled by one argument, creating a ”knob” to generate designs which possess the same functionality but do so in a varying number of clock cycles. Through industry standard tools all the created designs are synthesized and the energy consumption is simulated. The energy efficiency of the processor designs generated with the variable parallelism are compared to a fully dedicated FIR filter implementation.
Item Type:Essay (Master)
Clients:
Axign B.V., Enschede, Netherlands
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:53 electrotechnology
Programme:Electrical Engineering MSc (60353)
Link to this item:https://purl.utwente.nl/essays/90455
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