University of Twente Student Theses

Login

Design of a sub-1V bandgap reference in FinFET technology

Rossem, E. van (2009) Design of a sub-1V bandgap reference in FinFET technology.

[img]

PDF
1MB

Abstract:	The minimum feature size in CMOS technology decreases with newer generations to enable higher packing densities and higher speed of operation. As transistor dimensions become smaller and smaller the fundamental limiting factors of conventional CMOS are coming closer. One of the candidates to replace the conventional bulk technology is FinFET technology. One of the analog circuits that need to be implemented is the bandgap voltage reference circuit. The original bandgap reference outputs a voltage around the bandgap of a diode: 1.2V, independent of temperature. For implementations in the newer (low-voltage) CMOS processes the supply voltage is lower than this reference voltage which makes it impossible to use the conventional bandgap reference circuits. However, some solutions are known to implement bandgap reference circuits at low voltages, but all require a large total resistor value. In FinFET technology it is difficult to implement resistors and diodes. In this master assignment, an averaging bandgap reference structure is proposed to implement a low-supply voltage bandgap reference circuit in FinFET technology. The resistors that are typically required in known low-voltage bandgap references are replaced by a PTAT voltage source and a triode resistor. The PTAT voltage is made by cascaded voltage followers, with build-in PTAT off-sets. To make the triode resistor accurate over large voltage swings both a N-type and a P-type FinFET are used. These triode transistors need to be biased with a supply independent voltage. The output voltage is the average of a CTAT and a PTAT voltage, using two stages of transimpedance amplifiers. The simulated (layout) performance is: Vref = 565mV Sigma Vref = 0.42% Area = 0,084 mm2 Vdd > 0.85V The designed circuit is layouted, and is currently in fabrication in a 32 nm FinFET process at IMEC.
Item Type:	Essay (Master)
Faculty:	EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:	53 electrotechnology
Programme:	Electrical Engineering MSc (60353)
Link to this item:	https://purl.utwente.nl/essays/59419
Export this item as:	BibTeX EndNote HTML Citation Reference Manager

Show download statistics for this publication

Repository Staff Only: item control page